Abstract
To fully exploit the massive parallelism of many cores, this work tackles the problem of mapping large-scale applications onto heterogeneous on-chip networks (NoCs) to minimize the peak workload for energy hotspot avoidance. A task-resource co-optimization framework is proposed which configures the on-chip communication infrastructure and maps the applications simultaneously and coherently, aiming to minimize the peak load under the constraints of computation power and communication capacity and a total cost budget of on-chip resources. The problem is first formulated into a linear programming model to search for optimal solution. A heuristic algorithm is further developed for fast design space exploration in extremely large-scale many-core NoCs. Extensive simulations are carried out under real-world benchmarks and randomly generated task graphs to demonstrate the effectiveness and efficiency of the proposed schemes.
Original language | American English |
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Journal | 26th ACM International Conference on Great Lakes Symposium on VLSI (GLSVLSI) |
DOIs | |
State | Published - May 15 2016 |
Keywords
- Task-Resource Co-Allocation
- Many-Core NoC
- Hotspot Minimization
- Network-on-Chip (NoC)
Disciplines
- Computer Engineering
- Computer and Systems Architecture
- Hardware Systems
- Computer Sciences
- OS and Networks