Approximate Communication Strategies for Energy-Efficient and High Performance NoC: Opportunities and Challenges

With the advancement and miniaturization of transistor technology, hundreds of cores can be integrated on a single chip. Network-on-Chips (NoCs) are the de facto on-chip communication fabrics for multi/many core systems because of their benefits over the traditional bus in terms of scalability, parallelism, and power efficiency. However, relative power consumption of NoC has been increasing with the increase in the number of cores on a chip, as communication costs much more time and energy than that of computation. Approximating computing concept can be applied in the NoC to reduce power consumption by approximating the communication data of emerging data-intensive applications, such as machine learning and big data analytics, that can tolerate errors. In this paper, we present an architecture for NoC approximation, and also provide preliminary results (which shows significant improvement) to support the importance of approximate communication solution for energy-efficient and high-performance NoC. Then we present various approximate communication solutions for reducing data movement in NoC. Finally, we discuss about the challenges and software and hardware overheads to adapt approximate technique in NoC, and also provide tentative solutions to address those challenges.